Tunable crystal oscillators are used in communication systems to implement highly stable frequency sources with excellent spectral purity. These circuits are critical in digital communication systems such as high speed modems that require precision timing to achieve stringent bit error rate specifications.
FIG. 1 shows a typical application of tunable crystal oscillators in a simplified communication link consisting of a home modem, remote modem and a channel linking them. Each modem utilizes precision clocks and timing circuitry that is ultimately derived (using phase locked loops or other methods) from its own local tunable crystal oscillator.
Although these crystal based oscillators are very precise there still exists a slight frequency offset between the home and remote oscillators. This offset prevents data transmitted by one modem from being received by the other modem reliably unless some means is used to synchronize the receiver clock with the transmitter clock. The process of synchronizing the receiver clock to the transmitter clock is usually referred to as clock recovery. In the receiver, the clock recovery loop extracts timing information from the transmitted data and uses it to adjust the receiver local crystal oscillator until it matches the frequency and phase of the transmitter local oscillator A typical clock recovery loop block diagram that includes the tunable crystal oscillator is shown in FIG. 2. These loops may be implemented using a mix of digital and analog hardware. A portion of the loop may also be implemented as part of a software algorithm executing in a digital processor depending on the overall system constraints. The simplified clock recovery loop includes a tunable crystal oscillator in a feedback loop. When the feedback control signal to the local oscillator is a digital word it is desirable to utilize a digitally tuned crystal oscillator. The usual Pierce oscillator design, shown in FIG. 3, includes an inverting gain stage driving a phase shift network composed of a shunt capacitor on each side of the series branch crystal as shown in the Figure.
When the output of the phase shift network is fed back to the amplifier input, the circuit will oscillate at a frequency between .omega.s (series resonant frequency) and cop (parallel resonant frequency) of the crystal, assuming adequate loop gain. The oscillation frequency may be tuned (pulled) by changing the capacitance in the phase shift network. This can be done under EMF (voltage) control by replacing the fixed capacitors by varactor diodes to implement voltage variable capacitors. FIGS. 4A and 4B show typical digitally tuned crystal oscillator implementations based on the commonly used Pierce oscillator topology. Digital control is obtained by using a digital-to-analog converter to drive the varactor diode and results in the prior art topology of FIG. 4A. The varactor requires varied EMF (voltage) for control, and a separate digital-to-analog converter was used. The EMF ranges for the varactor are disadvantageous when constructing circuits designed for 3 volt operation. In this circuit, a digitally controlled Pierce oscillator uses an A/D converter and a varactor diode for frequency tuning. FIG. 4B shows the addition of an inductor in parallel with a varactor. Pierce oscillators are limited in their use on low voltage integrated circuits because:
1. To tune the oscillator over an adequate frequency range, say +/-125 ppm, the tuning capacitors change typically by a ratio of 10:1 or more. To achieve this variation in capacitance using varactor diodes requires a large range in tuning voltage, generally greater than 12V. This requirement is incompatible with modern low power communication systems constrained by 3.3V or lower supplies. PA1 2. The addition of the digital-to-analog converter adds considerable circuit complexity, consumes significant chip area, lowers manufacturing yield and increases cost and power consumption. PA1 3. Adequate tuning varactors are not available for most modern low cost, low voltage IC processes. This means they must be placed off chip, adversely impacting product size, cost, reliability and manufacturability.
As shown in FIG. 4B, it possible to use an inductor in parallel with the tuning capacitor (varactor). The parallel L-C network is designed to present an overall capacitive reactance near the oscillation frequency but achieves a higher reactance slope. The parallel L-C network exhibits faster reactance changes in response to changes in EMF. It is estimated that this technique may drop the tuning voltage requirement from 12 or more volts to about 5 volts, but this is still inadequate for inclusion in modern 0.351im and 0.25tm integrated circuit processes operating at 3.3V and 2.5V respectively. In addition to the problems outlined for the circuit of FIG. 3, this design also requires an off-chip inductor which adversely impacts size, cost, reliability and manufacturability. Prior art systems were difficult to configure in such a way as to meet the tuning requirements at 3.3V and below. Therefore, prior art systems consumed more power.
If a capacitance is used to tune the Pierce oscillator, the response of the Pierce oscillator tends to be nonlinear. This causes the device to exhibit instability, as the tuning becomes overly sensitive at some points and causes the device to exhibit low response at other points.